Hardware history - Revision history

Root: /* Era IV: Fourth Generation & Modern Computing (1974-Present) */

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Era IV: Fourth Generation & Modern Computing (1974-Present)

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	* '''Parallelism & Specialization''': Advanced techniques such as instruction pipelining, superscalar execution, hyper-threading, multi-core architectures, and specialized instruction sets (MMX, Streaming SIMD Extensions\|SSE) allow computers to process multiple instructions simultaneously.<br />		* '''Parallelism & Specialization''': Advanced techniques such as instruction pipelining, superscalar execution, hyper-threading, multi-core architectures, and specialized instruction sets (MMX, Streaming SIMD Extensions\|SSE) allow computers to process multiple instructions simultaneously.<br />

	=== Multicore Processors: Multiple ~~Cores~~ on a ~~Single Chip~~ ===		=== Multicore Processors: Multiple cores on a single chip ===
	A '''multicore processor''' packs two or more complete, independent central processing units (called '''cores''') onto a single piece of hardware, typically a single silicon chip or a small group of interconnected chip. Instead of running one single core at blisteringly high clock speeds (which produces excessive heat and draws too much power), CPU designers split the work across multiple cores running at efficient frequencies.<div class="mw-collapsible mw-collapsed" style="border:1px solid #ccc; padding:10px; background:#f9f9f9; border-radius:4px; margin-top:10px;">		A '''multicore processor''' packs two or more complete, independent central processing units (called '''cores''') onto a single piece of hardware, typically a single silicon chip or a small group of interconnected chip. Instead of running one single core at blisteringly high clock speeds (which produces excessive heat and draws too much power), CPU designers split the work across multiple cores running at efficient frequencies.<div class="mw-collapsible mw-collapsed" style="border:1px solid #ccc; padding:10px; background:#f9f9f9; border-radius:4px; margin-top:10px;">
	'''How do multiple cores fit and work on a single hardware piece?'''<div class="mw-collapsible-content" style="margin-top:8px;">		'''How do multiple cores fit and work on a single hardware piece?'''<div class="mw-collapsible-content" style="margin-top:8px;">

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	=== Step-by-Step Explanation ===		=== Step-by-Step Explanation ===
			'''1. Memory Segments (Data vs. Code)'''
	~~====~~ 1. Memory Segments (Data vs. Code) ~~====~~
	* <code>'''section .data'''</code>: Declares static, initialized memory.		* <code>'''section .data'''</code>: Declares static, initialized memory.
	** <code>hello db 'Hello, World!', 0Ah</code>: <code>db</code> stands for ''Define Byte''. It stores the ASCII characters in sequential memory addresses followed by <code>0Ah</code> (hexadecimal for decimal 10, the newline character <code>\n</code>).		** <code>hello db 'Hello, World!', 0Ah</code>: <code>db</code> stands for ''Define Byte''. It stores the ASCII characters in sequential memory addresses followed by <code>0Ah</code> (hexadecimal for decimal 10, the newline character <code>\n</code>).
	* <code>'''section .text'''</code>: Defines the memory area where executable CPU instructions live.		* <code>'''section .text'''</code>: Defines the memory area where executable CPU instructions live.
	* <code>'''global _start'''</code>: Informs the linker where the program execution begins (the program entry point, similar to <code>main()</code> in C).		* <code>'''global _start'''</code>: Informs the linker where the program execution begins (the program entry point, similar to <code>main()</code> in C).
			'''2. Preparing the Write System Call (Lines 9–14)'''

	~~==== 2. Preparing the Write System Call (Lines 9–14) ====~~
	To display text, the program asks the Linux kernel to run its internal `sys_write` routine. The kernel expects arguments loaded into specific CPU registers before execution:		To display text, the program asks the Linux kernel to run its internal `sys_write` routine. The kernel expects arguments loaded into specific CPU registers before execution:
	{\| class="wikitable"		{\| class="wikitable"
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	\| <code>'''int 80h'''</code> \|\| — \|\| '''Interrupt:''' Pauses user code execution and transfers control to the operating system kernel to perform the requested write operation.		\| <code>'''int 80h'''</code> \|\| — \|\| '''Interrupt:''' Pauses user code execution and transfers control to the operating system kernel to perform the requested write operation.
	\|}		\|}
			'''3. Clean program exit (Lines 16–20)'''

	~~==== 3. Clean program exit (Lines 16–20) ====~~
	In Assembly, execution does not stop automatically at the end of the file; without an explicit exit instruction, the CPU continues reading random adjacent memory as instructions, causing a crash (Segmentation fault).		In Assembly, execution does not stop automatically at the end of the file; without an explicit exit instruction, the CPU continues reading random adjacent memory as instructions, causing a crash (Segmentation fault).
	* <code>'''mov eax, 1'''</code>: Loads the system call number for <code>sys_exit</code> into <code>EAX</code>.		* <code>'''mov eax, 1'''</code>: Loads the system call number for <code>sys_exit</code> into <code>EAX</code>.

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 ** ''COBOL (Common Business-Oriented Language, 1959):'' Standardized by a committee guided by Grace Hopper, tailored for enterprise records, payroll, and business logic with English-like syntax.
 * '''The Role of compilers and interpreters:''' High-level source code cannot be executed directly by silicon logic. A translation layer—a ''compiler'' (translating entire programs to object/machine code ahead of execution) or an ''interpreter'' (evaluating statements dynamically line-by-line)—is required to map abstractions down to underlying machine cycles.
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Root: /* The Von Neumann Architecture (1945-1946) */

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The Von Neumann Architecture (1945-1946)

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	</div>		</div>

			<div class="mw-collapsible mw-collapsed" style="border: 1px solid #c8ccd1; background-color: #f8f9fa; padding: 12px; margin: 12px 0; border-radius: 4px;">
			'''Simple example: What machine language actually looks like (Adding 5 + 3)'''
			<div class="mw-collapsible-content" style="margin-top: 10px;">

			At its most basic level, a computer cannot read English words or complex code. It only understands numbers that turn tiny electronic switches on (1) or off (0).

			Here is a 5-byte program that adds the numbers 5 and 3:

			{\| class="wikitable" style="margin-top: 8px;"
			! Binary (What the chip sees) !! Hexadecimal !! What the CPU actually does !! Normal description
			\|-
			\| <code>10110000 00000101</code> \|\| <code>B0 05</code> \|\| Put the number 5 into memory slot <code>AL</code> \|\| Load first number
			\|-
			\| <code>00000100 00000011</code> \|\| <code>04 03</code> \|\| Add the number 3 to memory slot <code>AL</code> \|\| Add second number
			\|-
			\| <code>11110100</code> \|\| <code>F4</code> \|\| Stop working until told otherwise \|\| Halt (Stop)
			\|}

			'''The entire program in machine code is just 5 bytes:'''
			<pre>B0 05 04 03 F4</pre>

			* '''Step 1:''' The CPU reads <code>B0</code> and knows it must copy a number into its internal register. It reads <code>05</code> and stores 5.
			* '''Step 2:''' The CPU reads <code>04</code>, which triggers its adding circuit. It reads <code>03</code>, adds it to the 5 already stored, and gets 8.
			* '''Step 3:''' The CPU reads <code>F4</code> and halts.

			Before compilers and programming languages were invented, programmers had to write and debug long sequences of these exact numbers by hand.

			</div>
			</div>

	== Era III: Second and Third Generations (1958–1974) ==		== Era III: Second and Third Generations (1958–1974) ==

Root: /* The Von Neumann Architecture (1945-1946) */

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The Von Neumann Architecture (1945-1946)

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	# '''System Buses''': Communication pathways that transmit data, memory addresses, and control signals.		# '''System Buses''': Communication pathways that transmit data, memory addresses, and control signals.

			Simulador Von Neumann: https://www.youtube.com/watch?v=SBX9pma_e-g
	<div class="mw-collapsible mw-collapsed" style="border: 1px solid #a2a9b1; background-color: #f8f9fa; padding: 10px; margin: 10px 0; border-radius: 4px;">		<div class="mw-collapsible mw-collapsed" style="border: 1px solid #a2a9b1; background-color: #f8f9fa; padding: 10px; margin: 10px 0; border-radius: 4px;">
	'''Machine language: Hardware-level binary execution'''		'''Machine language: Hardware-level binary execution'''

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	Before conceiving the general-purpose Analytical Engine, '''Charles Babbage''' designed the '''Difference Engine''' (conceived in 1822) to address the rampant errors found in human-computed mathematical, astronomical, and navigation tables.		Before conceiving the general-purpose Analytical Engine, '''Charles Babbage''' designed the '''Difference Engine''' (conceived in 1822) to address the rampant errors found in human-computed mathematical, astronomical, and navigation tables.

	* '''Core ~~Purpose~~:''' Unlike the programmable Analytical Engine, the Difference Engine was a dedicated, fixed-function mechanical calculator designed to evaluate polynomial functions using the method of divided differences.		* '''Core purpose:''' Unlike the programmable Analytical Engine, the Difference Engine was a dedicated, fixed-function mechanical calculator designed to evaluate polynomial functions using the '''method of divided differences'''.
	* '''The ~~Method~~ of ~~Finite Differences~~:''' Because many mathematical functions (such as logarithms and trigonometric ratios) can be approximated by polynomials, calculation could be reduced entirely to simple, sequential additions without requiring multiplication or division:		* '''The method of finite differences:''' Because many mathematical functions (such as logarithms and trigonometric ratios) can be approximated by polynomials, calculation could be reduced entirely to simple, sequential additions without requiring multiplication or division:
	** $\Delta f(x) = f(x+h) - f(x)$		** $\Delta f(x) = f(x+h) - f(x)$
	** By storing starting values and constant higher-order differences on geared columns, rotating the main crank cascaded carries across decimal wheels to generate successive table entries automatically.		** By storing starting values and constant higher-order differences on geared columns, rotating the main crank cascaded carries across decimal wheels to generate successive table entries automatically.
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			<div class="mw-collapsible mw-collapsed" style="border: 1px solid #a2a9b1; background-color: #f8f9fa; padding: 10px; margin: 10px 0; border-radius: 4px;">
			'''Machine language: Hardware-level binary execution'''
			<div class="mw-collapsible-content" style="margin-top: 8px;">

			In first-generation electronic systems (Era II), computers possessed no operating systems or compilers; they executed programs encoded strictly in primitive binary machine instructions.

			* '''Nature of machine code:''' Machine code consists of raw hexadecimal or binary sequences (strings of 0s and 1s) directly decoded by the CPU’s control unit via digital logic gates.
			* '''Instruction structure:''' Each instruction maps directly to the underlying architecture and consists of:
			** ''Opcode (Operation code):'' Specifies the hardware operation (e.g., fetch memory, load accumulator, add register, jump).
			** ''Operands/Addresses:'' Specifies the target memory locations or hardware registers involved.
			* '''The First-generation programming experience:'''
			** Early systems like ENIAC originally required physically re-plugging patch cords and setting rotary switches to alter routines.
			** With stored-program systems (EDVAC, EDSAC), instructions were toggled manually via front-panel console switches or entered byte-by-byte into memory registers, resulting in extreme cognitive fatigue and tedious debugging.
			* '''Transition to assembly:''' The immense difficulty of reading raw binary prompted the creation of Assembly language (Second Generation), substituting numeric opcodes with human-readable mnemonics (e.g., <code>MOV</code>, <code>ADD</code>, <code>JMP</code>) that assembled 1-to-1 into machine instructions.

			</div>
			</div>


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	[[File:Transistors evolution.png\|thumb\|transistors evolution\|left\|268x268px]]		[[File:Transistors evolution.png\|thumb\|transistors evolution\|left\|268x268px]]
	[[File:Transistor 14nm.png\|none\|thumb\|transistor 14nm\|500x500px]]		[[File:Transistor 14nm.png\|none\|thumb\|transistor 14nm\|500x500px]]

			<div class="mw-collapsible mw-collapsed" style="border: 1px solid #a2a9b1; background-color: #f8f9fa; padding: 10px; margin: 10px 0; border-radius: 4px;">
			'''High-level language programs: abstraction over hardware'''
			<div class="mw-collapsible-content" style="margin-top: 8px;">

			Coinciding with the arrival of reliable transistor-based systems (Era III, 1958–1964), computing underwent a revolution by decoupling algorithm design from hardware instruction sets.

			* '''Hardware independence & abstraction:''' High-level programming languages (HLL) enable developers to write declarative mathematical expressions and algorithmic logic using English keywords, shielding programmers from specific register architectures and memory topologies.
			* '''Pioneering high-level languages:'''
			** ''FORTRAN (Formula Translation, 1957):'' Created by John Backus at IBM for scientific and numerical computation, proving that compiled code could match the execution speed of hand-crafted assembly.
			** ''LISP (List Processing, 1958):'' Pioneered symbolic computation, dynamic typing, and tree-based data structures for early artificial intelligence research.
			** ''COBOL (Common Business-Oriented Language, 1959):'' Standardized by a committee guided by Grace Hopper, tailored for enterprise records, payroll, and business logic with English-like syntax.
			* '''The Role of compilers and interpreters:''' High-level source code cannot be executed directly by silicon logic. A translation layer—a ''compiler'' (translating entire programs to object/machine code ahead of execution) or an ''interpreter'' (evaluating statements dynamically line-by-line)—is required to map abstractions down to underlying machine cycles.

			</div>
			</div>

	=== Third generation: Integrated circuits (1964–1974) ===		=== Third generation: Integrated circuits (1964–1974) ===
	The Third Generation did '''not''' replace the transistor. Instead, it solved the "Tyranny of Numbers" by replacing the physical wiring between transistors with chemical lithography on a single crystal slab. A frequent misconception is that integrated circuits replaced transistors; in reality, '''the transistor remained the fundamental building block of computing'''. The revolution lay in how transistors were manufactured, packaged, and connected: moving from individually wired components to micro-etched, monolithic semiconductor circuits.		The Third Generation did '''not''' replace the transistor. Instead, it solved the "Tyranny of Numbers" by replacing the physical wiring between transistors with chemical lithography on a single crystal slab. A frequent misconception is that integrated circuits replaced transistors; in reality, '''the transistor remained the fundamental building block of computing'''. The revolution lay in how transistors were manufactured, packaged, and connected: moving from individually wired components to micro-etched, monolithic semiconductor circuits.

	Invented independently by Jack Kilby (Texas Instruments, 1958) and Robert Noyce (Fairchild Semiconductor, 1959), the Integrated Circuit (IC) unified active components (transistors, diodes) and passive components (resistors, capacitors) into a single continuous substrate.		Invented independently by Jack Kilby (Texas Instruments, 1958) and Robert Noyce (Fairchild Semiconductor, 1959), the '''Integrated Circuit (IC)''' unified active components (transistors, diodes) and passive components (resistors, capacitors) into a single continuous substrate.

	'''How the IC transformed the transistor'''		'''How the IC transformed the transistor'''
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	** Each core has its own tiny, ultra-fast memory ('''L1 and L2 caches''') right next to its execution pipeline.		** Each core has its own tiny, ultra-fast memory ('''L1 and L2 caches''') right next to its execution pipeline.
	** All cores share a larger, central memory block on the same chip (the '''L3 cache'''), allowing them to pass data without having to travel across the motherboard to the main RAM.		** All cores share a larger, central memory block on the same chip (the '''L3 cache'''), allowing them to pass data without having to travel across the motherboard to the main RAM.
	* '''Data Highways (Interconnects):''' Cores are linked together by on-chip microscopic "highways" (such as a circular Ring Bus or a Grid/Mesh network) that let them swap information in nanoseconds.		* '''Data Highways (Interconnects):''' Cores are linked together by on-chip microscopic "highways" (such as a circular '''Ring Bus''' or a '''Grid/Mesh network''') that let them swap information in nanoseconds.
	'''3. Coordinated Execution (The Role of the OS)'''		'''3. Coordinated Execution (The Role of the OS)'''

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	* The OS task scheduler automatically assigns different applications (e.g., your web browser on Core 0 and a video game on Cores 1–4) to run concurrently.		* The OS task scheduler automatically assigns different applications (e.g., your web browser on Core 0 and a video game on Cores 1–4) to run concurrently.
	* When working on a single heavy application (like rendering 3D graphics or encoding video), the software splits the job into multiple smaller tasks (called threads), allowing all cores to work on parts of the same problem simultaneously.		* When working on a single heavy application (like rendering 3D graphics or encoding video), the software splits the job into multiple smaller tasks (called '''threads'''), allowing all cores to work on parts of the same problem simultaneously.

	{\| class="wikitable" style="margin-top:10px; width:100%;"		{\| class="wikitable" style="margin-top:10px; width:100%;"

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	[[File:Harvard Mark I.png\|thumb\|Harvard Mark I\|484x484px\|none]]		[[File:Harvard Mark I.png\|thumb\|Harvard Mark I\|484x484px\|none]]
	<div class="mw-collapsible mw-collapsed" style="border: 1px solid #a2a9b1; background-color: #f8f9fa; padding: 10px; margin: 10px 0; border-radius: 4px;">		<div class="mw-collapsible mw-collapsed" style="border: 1px solid #a2a9b1; background-color: #f8f9fa; padding: 10px; margin: 10px 0; border-radius: 4px;">
	'''Engineering & ~~Construction~~: How the Harvard Mark I was built'''		'''Engineering & construction: How the Harvard Mark I was built'''
	<div class="mw-collapsible-content" style="margin-top: 8px;">		<div class="mw-collapsible-content" style="margin-top: 8px;">

	Conceived by Harvard physicist '''Howard Aiken''' and engineered at IBM's Endicott laboratories under the direction of '''Clair D. Lake''', the IBM Automatic Sequence Controlled Calculator (ASCC / Harvard Mark I) translated Charles Babbage's purely mechanical concepts into electromechanical reality using standard tabulating machine components.		Conceived by Harvard physicist '''Howard Aiken''' and engineered at IBM's Endicott laboratories under the direction of '''Clair D. Lake''', the IBM Automatic Sequence Controlled Calculator (ASCC / Harvard Mark I) translated Charles Babbage's purely mechanical concepts into electromechanical reality using standard tabulating machine components.

	* '''Central ~~Drive Shaft~~ & Synchronized ~~Motion~~''':		* '''Central drive shaft & Synchronized motion''':
	** The machine was driven by a continuous '''5-horsepower electric motor''' connected to a single '''50-foot (15-meter) central driveshaft'''.		** The machine was driven by a continuous '''5-horsepower electric motor''' connected to a single '''50-foot (15-meter) central driveshaft'''.
	** This rotating steel driveshaft ran horizontally through the entire base of the machine, distributing mechanical rotational power to thousands of gears, cams, and counters via magnetic clutches.		** This rotating steel driveshaft ran horizontally through the entire base of the machine, distributing mechanical rotational power to thousands of gears, cams, and counters via magnetic clutches.

	* '''Standardized ~~Electromechanical Relays~~ & ~~Accumulators~~''':		* '''Standardized electromechanical relays & accumulators''':
	** Rather than using delicate experimental parts, IBM engineers assembled the machine using proven, mass-produced telephone relays, switches, and counter wheels from existing IBM punch-card accounting systems.		** Rather than using delicate experimental parts, IBM engineers assembled the machine using proven, mass-produced telephone relays, switches, and counter wheels from existing IBM punch-card accounting systems.
	** It contained '''72 accumulators''', each capable of holding a 23-decimal-digit number plus a sign indicator (+ or -). Mechanical carry wheels and electromechanical contacts executed arithmetic operations sequentially as the rotating shaft turned.		** It contained '''72 accumulators''', each capable of holding a 23-decimal-digit number plus a sign indicator (+ or -). Mechanical carry wheels and electromechanical contacts executed arithmetic operations sequentially as the rotating shaft turned.

	* '''Instruction ~~Control~~ via ~~Punched Paper Tape~~''':		* '''Instruction control via punched paper tape''':
	** Unlike later stored-program architectures, the Mark I read operational instructions sequentially from a wide, continuous '''24-channel perforated paper tape'''.		** Unlike later stored-program architectures, the Mark I read operational instructions sequentially from a wide, continuous '''24-channel perforated paper tape'''.
	** As the tape advanced line by line, metal contact fingers dropped through the holes to close electrical circuits, routing numbers from specific accumulator registers into the arithmetic unit and back.		** As the tape advanced line by line, metal contact fingers dropped through the holes to close electrical circuits, routing numbers from specific accumulator registers into the arithmetic unit and back.

	* '''Cabling & ~~Physical Housing~~''':		* '''Cabling & physical housing''':
	** Construction required over '''500 miles (800 km)''' of electrical wiring and thousands of terminal strips to interconnect relays and mechanical units.		** Construction required over '''500 miles (800 km)''' of electrical wiring and thousands of terminal strips to interconnect relays and mechanical units.
	** The entire 51-foot-long, 8-foot-tall frame was encased in a futuristic polished cabinet of stainless steel and glass designed by industrial designer Norman Bel Geddes, highlighting the synchronized motion of spinning mechanical wheels inside.		** The entire 51-foot-long, 8-foot-tall frame was encased in a futuristic polished cabinet of stainless steel and glass designed by industrial designer Norman Bel Geddes, highlighting the synchronized motion of spinning mechanical wheels inside.
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	{\| class="wikitable"		{\| class="wikitable"
	\|+Technical ~~Specifications~~ of the Harvard Mark I		\|+Technical specifications of the Harvard Mark I
	!Feature		!Feature
	!Specification		!Specification
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			<div class="mw-collapsible mw-collapsed" style="border: 1px solid #a2a9b1; background-color: #f8f9fa; padding: 10px; margin: 10px 0; border-radius: 4px;">
			'''Punched cards: The first external storage & Program input'''
			<div class="mw-collapsible-content" style="margin-top: 8px;">

			Punched cards represent the historical bridge between mechanical automation and digital data entry.

			* '''Origin in textiles (1804):''' Joseph Marie Jacquard revolutionized the textile industry by using perforated paperboard cards to control the needles on mechanical looms, automating the weaving of intricate tapestries.
			* '''Adaptation to computing (1830s):''' Charles Babbage and Ada Lovelace adapted Jacquard's concept for the Analytical Engine. Babbage divided cards into:
			** ''Operation cards:'' Directed the internal Mill on which arithmetic operation to execute (add, subtract, multiply, divide).
			** ''Variable cards:'' Dictated which storage registers (the "Store") supplied operands or accepted results.
			* '''Data processing & Herman Hollerith (1890):''' Herman Hollerith developed 80-column punched-card tabulators for the 1890 US Census, cutting computation time from ten years down to months. His company later merged to form IBM.
			* '''Role in 20th-Century computing:''' Punched cards served as the primary offline input/output medium for early mainframes through the 1970s. Programmers used keypunch machines (such as the IBM 029) where each card typically represented a single 80-character line of source code or record data.

			</div>
			</div>

Root: /* Comparison of Era 0 computing devices */

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Comparison of Era 0 computing devices

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	* '''Thomas de Colmar's Arithmometer (1820)''': The first mechanically reliable, commercially manufactured calculator capable of daily office use, bringing four-function desktop calculation into mass adoption across finance and engineering.[[File:Colmar arithmometer.png\|none\|thumb\|Colmar arithmometer]]		* '''Thomas de Colmar's Arithmometer (1820)''': The first mechanically reliable, commercially manufactured calculator capable of daily office use, bringing four-function desktop calculation into mass adoption across finance and engineering.[[File:Colmar arithmometer.png\|none\|thumb\|Colmar arithmometer]]

	* '''The Jacquard Loom (1804): The dawn of stored instruction''' In 1804, French weaver Joseph Marie Jacquard revolutionized textile production by automating loom operations through punched card chains. Perforated holes in stiff cards mechanically determined whether individual warp threads were lifted or lowered. While not designed for mathematical computation, Jacquard’s invention demonstrated the principle of '''external programmability''', the ability to change the machine's task dynamically by feeding it a new set of interchangeable cards without modifying the underlying physical machinery. This directly inspired Charles Babbage’s design for the Analytical Engine's card-reading mechanism. https://www.youtube.com/watch?v=pzYucg3Tmho		* '''The Jacquard Loom (1804): The dawn of stored instruction''' In 1804, French weaver Joseph Marie Jacquard revolutionized textile production by automating loom operations through punched card chains. Perforated holes in stiff cards mechanically determined whether individual warp threads were lifted or lowered. While not designed for mathematical computation, Jacquard’s invention demonstrated the principle of '''external programmability''', the ability to change the machine's task dynamically by feeding it a new set of interchangeable cards without modifying the underlying physical machinery. This directly inspired Charles Babbage’s design for the Analytical Engine's card-reading mechanism. Demonstration video: https://www.youtube.com/watch?v=pzYucg3Tmho
	[[File:Jacquard loom.png\|none\|thumb\|Jacquard loom]]		[[File:Jacquard loom.png\|none\|thumb\|Jacquard loom]]

Root at 10:26, 16 September 2026

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Show changes

Root: /* Comparison: Tubes vs. Discrete Transistors vs. Integrated Circuits */

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Comparison: Tubes vs. Discrete Transistors vs. Integrated Circuits

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	'''How the IC transformed the transistor'''		'''How the IC transformed the transistor'''
	* '''Monolithic integration:''' Instead of soldering individual transistors onto a board, dozens (SSI, Small-Scale Integration) and then hundreds (MSI, Medium-Scale Integration) of transistors were diffused and etched directly onto a single slice of silicon.		* '''Monolithic integration:''' Instead of soldering individual transistors onto a board, dozens (SSI, Small-Scale Integration) and then hundreds (MSI, Medium-Scale Integration) of transistors were diffused and etched directly onto a single slice of silicon.
	* '''Photolithography:''' Microscopic interconnects were deposited chemically (planar process) rather than wired by hand. The physical connection between transistors became part of the silicon ~~die~~ itself.		* '''Photolithography:''' Microscopic interconnects were deposited chemically (planar process) rather than wired by hand. The physical connection between transistors became part of the silicon chip itself.
	* '''Speed and physical distance:''' Because electrical signals propagate at a fraction of the speed of light (~20 cm/ns in copper traces), discrete systems lost processing time just waiting for signals to travel down copper traces. Compressing thousands of transistors into millimeters of silicon shortened signal travel times by orders of magnitude, dramatically increasing clock speeds.		* '''Speed and physical distance:''' Because electrical signals propagate at a fraction of the speed of light (~20 cm/ns in copper traces), discrete systems lost processing time just waiting for signals to travel down copper traces. Compressing thousands of transistors into millimeters of silicon shortened signal travel times by orders of magnitude, dramatically increasing clock speeds.
	* '''Economic scaling:''' Batch fabrication meant an entire wafer containing hundreds of ICs, each holding thousands of transistors, could be produced simultaneously, dropping the per-transistor manufacturing cost from dollars to fractions of a cent.		* '''Economic scaling:''' Batch fabrication meant an entire wafer containing hundreds of ICs, each holding thousands of transistors, could be produced simultaneously, dropping the per-transistor manufacturing cost from dollars to fractions of a cent.
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	=== Multicore Processors: Multiple Cores on a Single Chip ===		=== Multicore Processors: Multiple Cores on a Single Chip ===
	A '''multicore processor''' packs two or more complete, independent central processing units (called '''cores''') onto a single piece of hardware, typically a single silicon ~~die~~ or a small group of interconnected ~~dies~~. Instead of running one single core at blisteringly high clock speeds (which produces excessive heat and draws too much power), CPU designers split the work across multiple cores running at efficient frequencies.<div class="mw-collapsible mw-collapsed" style="border:1px solid #ccc; padding:10px; background:#f9f9f9; border-radius:4px; margin-top:10px;">		A '''multicore processor''' packs two or more complete, independent central processing units (called '''cores''') onto a single piece of hardware, typically a single silicon chip or a small group of interconnected chip. Instead of running one single core at blisteringly high clock speeds (which produces excessive heat and draws too much power), CPU designers split the work across multiple cores running at efficient frequencies.<div class="mw-collapsible mw-collapsed" style="border:1px solid #ccc; padding:10px; background:#f9f9f9; border-radius:4px; margin-top:10px;">
	'''How do multiple cores fit and work on a single hardware piece?'''<div class="mw-collapsible-content" style="margin-top:8px;">		'''How do multiple cores fit and work on a single hardware piece?'''<div class="mw-collapsible-content" style="margin-top:8px;">
	Fitting multiple CPU cores onto a single piece of silicon requires three key hardware solutions:		Fitting multiple CPU cores onto a single piece of silicon requires three key hardware solutions:

	'''1. Physical ~~Layout~~ on the ~~Silicon Die~~'''		'''1. Physical layout on the silicon chip'''
	* '''Photolithography:''' Millions (or billions) of microscopic transistors are etched directly into one continuous piece of silicon using light. A modern 4-core, 8-core, or 16-core chip simply etches several complete CPU processing units side-by-side on that same slice of silicon.		* '''Photolithography:''' Millions (or billions) of microscopic transistors are etched directly into one continuous piece of silicon using light. A modern 4-core, 8-core, or 16-core chip simply etches several complete CPU processing units side-by-side on that same slice of silicon.
	* '''Monolithic vs. Chiplets:'''		* '''Monolithic vs. Chiplets:'''
	** ''Monolithic Design:'' All cores, memory controllers, and caches are etched onto one single slab of silicon (common in laptops and smartphones).		** ''Monolithic Design:'' All cores, memory controllers, and caches are etched onto one single slab of silicon (common in laptops and smartphones).
	** ''Chiplet Design:'' Several smaller silicon tiles (each containing multiple cores) are placed on the same fiberglass substrate and connected via microscopic high-speed bridges (popularized by AMD Ryzen and modern enterprise chips).		** ''Chiplet Design:'' Several smaller silicon tiles (each containing multiple cores) are placed on the same fiberglass substrate and connected via microscopic high-speed bridges (popularized by AMD Ryzen and modern enterprise chips).
	'''2. Shared ~~Memory~~ and On-~~Chip Interconnects~~'''		'''2. Shared memory and on-chip interconnects'''

	If cores were completely isolated, they couldn't coordinate. They share space and communicate using an on-chip network:		If cores were completely isolated, they couldn't coordinate. They share space and communicate using an on-chip network:
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	* '''Layered Caches:'''		* '''Layered Caches:'''
	** Each core has its own tiny, ultra-fast memory ('''L1 and L2 caches''') right next to its execution pipeline.		** Each core has its own tiny, ultra-fast memory ('''L1 and L2 caches''') right next to its execution pipeline.
	** All cores share a larger, central memory block on the same ~~die~~ (the '''L3 cache'''), allowing them to pass data without having to travel across the motherboard to the main RAM.		** All cores share a larger, central memory block on the same chip (the '''L3 cache'''), allowing them to pass data without having to travel across the motherboard to the main RAM.
	* '''Data Highways (Interconnects):''' Cores are linked together by on-chip microscopic "highways" (such as a circular Ring Bus or a Grid/Mesh network) that let them swap information in nanoseconds.		* '''Data Highways (Interconnects):''' Cores are linked together by on-chip microscopic "highways" (such as a circular Ring Bus or a Grid/Mesh network) that let them swap information in nanoseconds.
	'''3. Coordinated Execution (The Role of the OS)'''		'''3. Coordinated Execution (The Role of the OS)'''
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	{\| class="wikitable" style="margin-top:10px; width:100%;"		{\| class="wikitable" style="margin-top:10px; width:100%;"
	!Component		!Component
	!Role on the ~~Single~~ CPU ~~Die~~		!Role on the single CPU chip
	\|-		\|-
	\|'''Individual Core'''		\|'''Individual Core'''
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	\|-		\|-
	\|'''Shared Cache (L3)'''		\|'''Shared Cache (L3)'''
	\|Common pool of memory on the ~~die~~ that all cores read from.		\|Common pool of memory on the chip that all cores read from.
	\|-		\|-
	\|'''Internal Interconnect'''		\|'''Internal Interconnect'''